Faculty:
            Name                  Academic Department
Dr. Katkoori, Srinivas Department of Computer Science and Engineering
Dr. Nagarajan, Ranganathan Department of Computer Science and Engineering
Dr. Bhanja, Sanjukta Department of Electrical Engineering
Dr. Bhansali, Shekhar  Department of Electrical Engineering
Dr. Dunleavy, Lawrence Department of Electrical Engineering
Dr. Jain, Vijay Department of Electrical Engineering
Dr. Moreno, Wilfrido Department of Electrical Engineering
Dr. Saddow, Stephan Department of Electrical Engineering
Dr. Weller, Thomas Department of Electrical Engineering
Students:
Name Degree Expected Research Area Advisor Cadence Suite
Narender Hanchate Ph.D. 2006 Interconnect optimization using wire-sizing/spacing and crosstalk optimization Dr. Ranganathan DSM, SOC, Virtuoso, CADMOS
Viswanath Sairaman Ph.D. 2006 Hardware software co-design, partitioning and task scheduling Dr. Ranganathan SOC, LDV
Upavan Gupta Ph.D. 2007 Design automation, power and delay optimization Dr. Ranganathan LDV, DSM, SOC, Virtuoso
Suvodeep Gupta Ph.D. 2004 Developing feedback driven crosstalk optimization algorithms during high level synthesis Dr. Katkoori DSM, SOC, Virtuoso
Vyas Krishnan Ph.D. 2006 Genetic algorithms for high level synthesis Dr. Katkoori LDV, Virtuoso
Hao Li Ph.D. 2005 FPGA low power synthesis Dr. Katkoori LDV, DSM, Virtuoso
Shailaja P Rao Ph.D. 2005 To design the masks that is used for the device fabrications Dr. Saddow Virtuoso
Jeremy Walker Ph.D. 2006 HV Electronics design using schematic capture, layout and simulation Dr. Saddow Analog Artist, Capture, Virtuoso
Thara Rejimon Ph.D. 2006 VLSI testing, crosstalk estimation, testing for crosstalk and delay faults in DSM Dr. Bhanja CADMOS, DSM, Virtuoso
Karthikeyan Lingasubramanian Ph.D. 2007 VLSI design automation, mixed signal, nanotechnology Dr. Bhanja LDV, Virtuoso, DSM
Saket Srivastava Ph.D. 2007 Design and developement of VLSI based expert systems Dr. Bhanja LDV, DSM, Virtuoso
Hariharan Sankaran Masters 2004 Synthesis of an ASIC for mobile computing Dr. Katkoori LDV, DSM, Virtuoso
Umadevi Kailasam Masters 2004 Power Optimization in an ASIC for mobile computing Dr. Katkoori LDV, DSM, Virtuoso
Vishwanath Daita Masters 2004 Behavioral modeling of a GPS digital receiver Dr. Katkoori LDV
Anulekha Bilhanan Masters 2004 Hardware implementation of cancer detection algorithms using digitized mammograms Dr. Katkoori LDV
Pradeep Fernando Masters 2004 Design automation for 3D ICs Dr. Katkoori Virtuoso, DSM, LDV
Matthew Calderon Masters 2004 Fast and Efficient Algorithms for Behavioral Synthesis Dr. Katkoori LDV
Nirmal Ramalingam Masters 2004 Power estimation using bayesian networks Dr. Bhanja LDV, SOC
Shiva Shankar Ramani Masters 2004 Anytime power estimates (simulation based) and design Dr. Bhanja LDV, Virtuoso, DSM
Satish Kumar Ponraj Masters 2004 RTL level probabilistic models Dr. Bhanja LDV
Research Labs / Groups:
Name          Location
VLSI, Computer Architecture and Parallel Processing (VCAPP) Research Group ENB222 and ENB224
VLSI Testing and Design (VDAT) Research Group ENB349a
Recent Ph.D. Dessertation:
Name Dessertation Title Advisor Year Cadence tools used
Ashok Murugavel New Methods for Dynamic Power Estimation and Optimization in VLSI Circuits Dr. Ranganathan 2003 Virtuoso, DSM, LDV
Saraju Mohanty Energy and Transient Power Minimization During Behavioral Synthesis Dr. Ranganathan 2003 LDV, Virtuoso
Stelian Alupoaei Net Clustering Based Macrocell Placement Techniques for Wirelength Minimization in DSM Regime Dr. Katkoori 2003 DSM, Virtuoso
Chandramouli Gopalakrishnan High Level Techniques for Leakage Power Estimation and Optimization in VLSI ASICs Dr. Katkoori 2003 Virtuoso, LDV
Recent Masters Thesis:
Name Thesis Title Advisor Year Cadence tools used
Ananth Durbha A Novel Route-and-Place RTL Design Methodology for Interconnect Optimization in DSM Regime Dr. Katkoori 1999 DSM, LDV, Virtuoso
Smitha Myneni Development of an Accurate Power Simulator using hierarchical VHDL Specifications Dr. Katkoori 2000 LDV
Chandramouli Gopalakrishnan Power Optimization via Input Transformations Dr. Katkoori 2000 DSM, Virtuoso
Suvodeep Gupta Force-directed Scheduling for Dynamic Power Optimization Dr. Katkoori 2002 DSM, LDV, Virtuoso
Praveen Samudrala Single-Event Upset (SEU) tolerant FPGA synthesis Dr. Katkoori 2003 DSM, LDV, Virtuoso
Narender Hanchate LECTOR: A Technique for Leakage Reduction in CMOS Circuits Dr. Ranganathan 2003 DSM, Virtuoso
Prashant Dongale Force-Directed Instruction Scheduling for Low Power Embedded Systems Dr. Ranganathan 2003 LDV
Praveen Bamini Implementation of a Speech Synthesis System Dr. Katkoori 2003 LDV