1. CIS 6930 005 Digital CMOS VLSI Design: The course objective is to make a student understand the basics of CMOS technology, various CMOS design styles and deep submicron issues. In this course, the students are exposed to state-of-the-art CAD tools like Cadence Virtuoso Schematic Editor, Cadence Virtuoso Layout Editor, Synopsys HSPICE through various hands-on assignments. As a final project, the students design the layout of an ASIC using Virtuoso Layout Editor and get them fabricated using the Mosis service.

2. CIS 6930 007 Low Power CMOS VLSI Design and CAD: Excessive power dissipation in modern microprocessors and limited power budget for high performance portable electronics have underlined the need for low power VLSI design methodologies. To make the student a power conscious VLSI designer - is the sole objective of this course. It will be achieved by: low power design exercises using Cadence IC suite, LDV suite, DSM SE suite, Synopsys HSPICE, IRSIM, and other state-of-the-art CAD tools, an extensive literature survey, and a project (involves implementing three popular low power techniques using Cadence Silicon Ensemble and Virtuoso Layout Editor).

3. CIS 4930 004/CIS 6930 006 Digital Circuit Synthesis: In order to handle the Very Large Scale Integration (VLSI) level complexity in modern IC's, high level design automation tools are quintessential. In this course, the student will be trained in using high-level synthesis (HLS) tools to automatically produce working chips. Some of the tasks that will be assigned are: developing module library in VHDL, verifying the design using Cadence LDV suite, coding a synthesis algorithm in C/C++, using an HLS system to synthesize a design, etc. Cadence LDV tools and AUDI, a high-level synthesis system developed by Dr. S. Katkoori's research group, will be used extensively in this course.

4. CDA 4203 004 Computer Systems and Logic Design:

1. EEL 5344 Digital CMOS VLSI Design: The course objective is to make a student a skilled VLSI designer. The course deals with MOS transistor theory, CMOS processing technology, circuit characterization and performance estimation, CMOS design styles, clocking strategies, design methods and tools, CMOS design examples and case studies. The students are exposed to state-of-the-art CAD tools like Cadence IC suite, DSM SE suite, Synopsys HSPICE.

2. EEL 6936 Low Power VLSI Design: In recent years, enormous growth has occurred in terms portability of the computation. Computing demands from battery operated devices are increasing rapidly. This course is targeted to capture all the information regarding the existing techniques and future challenges for CMOS VLSI design that consumes low power. You would require to use Cadence LDV, DSM, Virtuoso tool suite and HSPICE. The first assignment involves various techniques for sequential circuit power estimates, the second assignment would involve different logic families and their effect on power and the third assignment would handle a non-linear cell design and power optimization on the same.

3. EEL 6936 Analog RFIC Design: To learn radio frequency integrated circuit design techniques in the context of Silicon Microelectronic implementations. The first half of the class will focus on traditional analog design, while the second half of the class will focus on RF circuit implementations. This course presents the design theory, technology, and applications of Silicon-based analog radio frequency circuit (RFIC) technology. Lectures, homework, and CAD projects develop the understanding of the design, processing, and performance issues for RFICs. Agilent Advanced Design System (ADS) integrated with Cadence Analog IC suite are used to design the RFICs.

4. EEL 6936 Advanced Analog RFIC Design: Presents advanced design theory, technology, and applications of silicon-based analog radio frequency integrated circuit (RFIC) technology. Lectures, homework and CAD projects develop understanding of the processing, design, and performance issues for RFICs including system to layout with a SiGe fabrication goal. Advanced RFIC technology, transceiver architectures; Tx/Rx system applications; Si and SiGe devices; noise, LNAs; mixers; oscillators; synthesizers; and power amplifiers, RFIC system design, RFIC package modeling, internal ESD protection circuits for IC's, detailed IC layout using Cadence design kit devices and 4 level metal interconnects and bondpads, Layout Vs Schematic (LVS) and Design Rule Checking (DRC) checking using Cadence.